1. Field of the Invention
The invention relates to a transistor switch control circuit. Particularly, the invention relates to a transistor switch control circuit capable of preventing a short through phenomenon.
2. Description of Related Art
In a synchronous driving circuit, a problem most in need of attention is that a time for conducting a high-side transistor is overlapped to a time for conducting a low-side transistor to cause a short through phenomenon. In order to avoid the above problem, a dead time is set between two signals of controlling the high-side transistor and the low-side transistor. However, due to different characteristics of the transistors, the dead time required to be set is also different. If the dead time is set to a longer time, most of the transistors are matched, though a whole efficiency is decreased. On the other hand, if the dead time is set to a shorter time, some transistors may have the short through problem. In order to achieve a self-adjust ability of the synchronous driving circuit in collaboration with the transistors, a commonly used method is to detect a driving signal to confirm whether the other transistor is indeed turned off before the driving circuit turns on the corresponding transistor, so as to avoid the short through phenomenon.
Referring to FIG. 1, FIG. 1 is a circuit schematic diagram of a conventional synchronous driving circuit. The synchronous driving circuit, including RS flip-flops 10 and 20, and inverters 5, 15 and 25, is used to drive a buck converter according to a duty cycle control signal Spwm. The buck converter includes a high-side transistor Q1, a low-side transistor Q2, an inductor L and a capacitor C, and is used for converting an input voltage Vin into an output voltage Vout. The duty cycle control signal Spwm is respectively inputted to an S terminal of the RS flip-flop 10 and, through the inverter 5, an S terminal of the RS flip-flop 20. The RS flip-flops 10 and 20 respectively generate a high-side control signal HDRV and a low-side control signal LDRV through the inverters 15 and 25 to turn on the corresponding high-side transistor Q1 and the low-side transistor Q2. FIG. 2 is a circuit schematic diagram of a conventional RS flip flop, which is formed by two NAND gates. Therefore, when the R terminal of the RS flip-flop 10 or 20 receives a high logic level signal, the Q terminals thereof maintain their original outputs. Referring to FIG. 1, the R terminal of the RS flip-flop 10 receives the low-side control signal LDRV, and the R terminal of the RS flip-flop 20 receives the high-side control signal HDRV. Therefore, only after the signal received by the R terminal of the RS flip-flop 10 or 20 is transited from the high logic level to the low logic level, the output logic level of the Q terminal is changed according to the duty cycle control signal Spwm. In other words, only when the high-side transistor Q1 is turned off (the high-side control signal HDRV is at the low logic level), the RS flip-flop 20 may turn on the low-side transistor Q2, or only when the low-side transistor Q2 is turned off (the low-side control signal LDRV is at the low logic level), the RS flip-flop 10 may turn on the high-side transistor Q1.
However, the above situations are ideal situations without considering delay of each of the circuit modules. In an application environment that the high-side transistor Q1 and the low-side transistor Q2 are all N-type metal-oxide-semiconductor field-effect transistors, in order to successfully turn on the high-side transistor Q1, a bootstrap circuit is additionally added. Referring to FIG. 3, FIG. 3 is a circuit schematic diagram of another conventional synchronous driving circuit. Compared to the buck converter of FIG. 1, a bootstrap circuit 70 is added to provide a suitable driving level to the inverter 15 according to a potential of a connecting point between the high-side transistor Q1 and the low-side transistor Q2 and the input voltage Vin, so that the high-side control signal HDRV generated by the inverter 15 can indeed turn on the high-side transistor Q1. To ensure that logical operations among the RS flip-flops 10 and 20 and the inverter 15, level shifters (or level detectors) 45 and 50 are respectively added between the RS flip-flop 10 and the inverter 15 and between the RS flip-flop 20 and the inverter 15. The level shifters and the level detectors have a larger time delay compared to other circuits, and such time delay may cause misjudgement on the duty cycle control signal Spwm having a short duty cycle.
Referring to FIG. 4, FIG. 4 is a signal waveform diagram of the synchronous driving circuit of FIG. 3. Compared to the time delay of the level shifter, the time delays of the RS flip-flop and the inverter are relatively small, so that the time delays of the RS flip-flops and the inverters can be neglected. A delay time dt1 exists between the duty cycle control signal Spwm and an output signal S45 of the level shifter 45, and a delay time dt2 exists between the output signal S45 of the level shifter 45 and the output signal S50 of the level shifter 50. Therefore, referring to a left part of FIG. 4 and referring to FIG. 3, when the duty cycle control signal Spwm is transited to the high level, the inverter 5 outputs an output signal S5 of the low level, and triggers the RS flip-flop 20 to output an output signal S20 of the high level through the Q terminal. The inverter 25 inverts the output signal S20 and outputs the low-side control signal LDRV of the low level to turn off the low-side transistor Q2. After the delay time dt1, the output signal S45 of the level shifter 45 is transited to the low level, and the inverter 15 inverts the output signal S45 and outputs the high-side control signal HDRV of the high level to turn on the low-side transistor Q1. Then, after the delay time dt2, the output signal S50 of the level shifter 50 is transited to the high level. When the duty cycle control signal Spwm is transited to the low level, the inverter 5 inverts to output the output signal S5 of the high level. Meanwhile, the RS flip-flop 10 is triggered to generate a high level signal at the Q terminal. After the delay time dt1, the output signal S45 of the level shifter 45 is transited to the high level, and the inverter 15 inverts the output signal S45 and outputs the high-side control signal HDRV of the low level to turn off the low-side transistor Q1. The RS flip-flop 20 is triggered to output the output signal S20 of the low level through the Q terminal. Then, after the delay time dt2, the output signal S50 is transited to the low level to trigger the RS flip-flop 20 to output the output signal S20 of the low level through the Q terminal. The inverter 25 inverts the output signal S20 to output the low-side control signal LDRV of the high level, so as to turn on the low-side transistor Q2.
However, referring to a right part of FIG. 4 and referring to FIG. 3, when the duty cycle control signal Spwm has a short duty cycle, the duty cycle is transited from the low level to the high level and is again transited to the low level, due to the time delays of the level shifters 45 and 50, the output signal S50 is still maintained to the low level. Now, the inverter 5 outputs the high level signal, so that the RS flip-flop 20 outputs the low level signal and the inverter 25 outputs the low-side control signal LDRV of the high level to turn on the low-side transistor Q2. Then, the output signal S45 is transited to the low level, and the inverter 15 inverts the output signal S45 of the low level to output the high-side control signal HDRV of the high level to turn on the high-side transistor Q1. Therefore, the high-side transistor Q1 and the low-side transistor Q2 are simultaneously turned on for a time length st (i.e. a time length of the short duty cycle of the duty cycle control signal Spwm), which may cause the short through phenomenon.